1. Field of the Invention
The present invention relates to a memory tester for verifying operations of a semiconductor memory by detecting whether or not a predetermined expected value is sent back when a predetermined signal is supplied to the semiconductor memory.
2. Description of the Background Art
A memory tester and a logic tester exemplify a semiconductor integrated circuit testing apparatus for testing a semiconductor integrated circuit such as a memory or a logic LSI (large scale integration). As indicated by their names, a memory tester is an apparatus for testing whether or not a memory operates normally, and a logic tester is an apparatus for testing whether or not a logic LSI operates normally.
On the other hand, semiconductor integrated circuits for image processing and for mobile communications are desired to have the capability of processing both of an analog signal and a digital signal. Thus, an analog/digital mixed LSI (mixed signal LSI) containing an analog signal processing part and a digital signal processing part is employed for such circuits. The mixed signal LSI is generally provided with a digital-to-analog converter for converting a digital signal into an analog signal and an analog-to-digital converter for converting an analog signal into a digital signal.
To test a device having the analog-to-digital (A/D) converting function and digital-to-analog (D/A) converting function such as the mixed signal LSI, an analog signal as well as a digital signal needs to be used. Thus, a mixed signal tester capable of outputting both of digital and analog signals is employed for this purpose.
FIG. 10 illustrates an exemplary structure of such mixed signal tester. A mixed signal tester T2 comprises: a control unit 10; a digital-to-analog (D/A) converter 11 for converting a digital signal S10 output from the control unit 10 into an analog signal S11 and outputting the signal to the outside; and an analog-to-digital (A/D) converter 12 for converting an analog signal S14 input from the outside into a digital signal S15 and outputting the signal to the control unit 10.
The control unit 10, which represents a central processing unit (CPU) or a digital signal processor (DSP) to which storing means (e.g., a read-only memory (ROM) and a random access memory (RAM)) is connected, is a functional component operated by predetermined software programs stored in the ROM and RAM. The control unit 10 controls the D/A converter 11 and the A/D converter 12, while exchanging a digital signal S12 with the outside via another path different from one leading to the D/A converter 11.
A device under test (DUT) 200 serving as the mixed signal LSI is connected to the mixed signal tester T2 through pin electronics PE. The pin electronics PE serve as an interface circuit for transmitting a signal from the mixed signal tester T2 to each pin of the DUT 200 and an output signal from each pin of the DUT 200 to the mixed signal tester T2. The pin electronics PE generally comprise, per pin, a driver DR for controlling a signal from the mixed signal tester T2 and a comparator CP for detecting whether an output signal from each pin of the DUT 200 has a value greater (or smaller) than a predetermined value.
To operate the driver DR and the comparator CP, a voltage source VS is provided, whose potentials at its both terminals are indicated by first and second reference potentials V1 and V2, respectively.
FIG. 11 illustrates an exemplary structure of the comparator CP. The comparator CP includes a High-side comparator C1 and a Low-side comparator C2. One side input terminals of the High-side comparator C1 and the Low-side comparator C2 are both supplied with an output signal S13 from the DUT 200. The other input terminal of the High-side comparator C1 is supplied with the first reference potential V1 through a High-side pad P1, and that of the Low-side comparator C2 is supplied with the second reference potential V2 through a Low-side pad P2.
Output signals S12a and S12b of the High-side comparator C1 and the Low-side comparator C2 are transmitted to the control unit 10, respectively, as the digital signal S12. The control unit 10 judges whether a malfunction occurs in the DUT 200 in accordance with the transmitted result. In the case that the signal S13 from the DUT 200 is an analog signal and thus no comparison need to be made at the comparator CP, the analog signal is output as the signal S14 from the pin electronics PE to the A/D converter 12 included in the mixed signal tester T2.
The mixed signal tester is capable of processing both digital and analog signals 15 and thus have improved convenience, whereas it is expensive due to the complexity of its device structure and that of information processing performed therein.
On the other hand, a memory tester, which processes a digital signal alone, is inexpensive because of its simple device structure and simple information processing compared to those of the mixed signal tester. However, the memory tester is incapable of processing an analog signal, and thus, incapable of testing a device having the A/D converting function and D/A converting function such as the mixed signal LSI.
FIG. 12 illustrates an exemplary structure of the memory tester. The memory tester T1c comprises: a control unit 1; an algorithmic pattern generator (ALPG) 2 for generating, on the basis of vector data VD, a test pattern as a digital signal to be supplied to a memory cell in each address in a DUT 300 serving as a memory; and a fail bit analyzer (FBA) 3 for analyzing a failure position in the DUT 300 when a failure is found in an output of the DUT 300, thereby replacing the failure position with a redundant circuit included in the DUT 300.
The control unit 1, which represents a CPU or a DSP to which storing means (e.g., ROM and RAM) is connected, is a functional component operated by predetermined software programs stored in the ROM and RAM. The control unit 1 controls the ALPG 2 and the FBA 3.
The DUT 300 is connected to the memory tester T1c through the pin electronics PE similar to those illustrated in FIG. 10. Each of signals from the ALPG 2 (an address signal S1a and a data signal S1b, both of which are 8-bit digital signals, for example) is transmitted to the DUT 300 through the pin electronics PE as a signal S2.
FIG. 13 is a flow chart showing an operation of the memory tester T1c. First, a test pattern to be supplied to the DUT 300 is designated as vector data VD and is input to the control unit 1 (step ST1). The vector data here represents data for designating what type of data (e.g., xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d) is to be stored in each of a plurality of memory cells arranged in row and column directions in the DUT 300.
Concrete examples of the vector data VD are shown in FIGS. 14 and 15. FIG. 14 shows an example of vector data that designates the contents of data for each memory cell by xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d in binary. FIG. 15 shows another example of vector data that designates the contents of data for each memory cell by applying a predetermined rule.
The respective vector data shown in FIGS. 14 and 15, whose X (row) addresses and Y (column) addresses are designated by, e.g., 8 bits, respectively, have data patterns like a checker flag (in which data is aligned with the contents inverted alternatingly as xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d . . . both in the X and Y directions). The vector data shown in FIG. 14 has the data contents inverted alternatingly as xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d . . . in the same Y address as the X addresses increase one by one. Invoked in the vector data shown in FIG. 15 is a program having a pattern name of CHK in which an algorithm for previously generating a pattern like a checker flag (e.g., algorithm for inputting data xe2x80x9c1xe2x80x9d to memory cells having X and Y addresses both in odd coordinates and those having X and Y coordinates both in even coordinates, while inputting data xe2x80x9c0xe2x80x9d to other memory cells) is stored.
The ALPG 2 exchanges a signal S0 with the control unit 1, thereby receiving controlling information and information on vector data VD from the control unit 1 and providing the control unit 1 with information on the operating condition thereof. The ALPG 2 then generates a test pattern on the basis of the vector data VD (step ST2), and supplies the pattern to the DUT 300 (step ST3c). More specifically, the ALPG 2 supplies the address signal S1a and the data signal S1b to the DUT 300 as the signal S2 through the pin electronics PE. Although illustration is omitted, the ALPG 2 also outputs a control signal to the DUT 300.
On the other hand, the signal S2 includes a signal output from the DUT 300 to the pin electronics PE. The output signal is input to the FBA 3 through the pin electronics PE as a signal S5.
The FBA 3 analyzes a failure position. The result of analysis is supplied to the control unit 1 as a signal S6 together with the output signal of the DUT 300. The control unit 1 verifies whether the output signal from the DUT 300 is in accordance with 20 the test pattern generated in the ALPG 2 (step ST4c).
It is desirable that a digital tester such as the above-described memory tester be capable of testing a device having the A/D converting function and D/A converting function such as the mixed signal LSI.
An object of the present invention is to provide a test system and a testing method capable of testing the A/D converting function or D/A converting function of a device under test using a memory tester which is less expensive than a mixed signal tester.
A first aspect of the present invention is directed to a test system. The test system includes a memory tester and a digital-to-analog converter. The memory tester includes a test pattern generating section for generating a predetermined test pattern to be supplied to a memory cell in each address in a memory device and a control unit for controlling the test pattern generating section. The digital-to-analog converter is one of digital-to-analog converters, one built in the memory tester and the other provided outside the memory tester. In the test system, the control unit is supplied with vector data for generating the predetermined test pattern. The test pattern generating section generates the predetermined test pattern on the basis of the vector data. A test digital signal included in the predetermined test pattern is converted into a test analog signal by the digital-to-analog converter to be supplied to a device under test having the analog-to-digital converting function. And the control unit compares the test digital signal with an output digital signal generated in the device under test by converting the test analog signal, thereby verifying the analog-to-digital converting function of the device under test.
In the test system, the test digital signal included in the predetermined test pattern is converted into the test analog signal by the digital-to-analog converter and to be supplied to the device under test. The control unit compares the test digital signal with the output digital signal generated in the device under test by converting the test analog signal, thereby verifying the analog-to-digital converting function of the device under test. This allows the memory tester to perform testing of the analog-to-digital converting function of the device under test.
Preferably, the test system further includes a storage device for storing the output digital signal and outputting the signal to the control unit.
In the test system, the storage device for storing the output digital signal and outputting the signal to the control unit is further provided. Thus, the control unit does not need to make a real-time comparison between the output digital signal and the test digital signal.
Preferably, in the test system, the storage device is a memory provided in a fail bit analyzer for analyzing a failure position in the memory device when a failure is found in an output of the memory device.
In the test system, the storage device is the memory provided in the FBA. Thus, there is no need to provide an additional storage device for the memory tester, but the memory provided inside the FBA which is generally built in the memory tester can be diverted for the storage device.
Preferably, in the test system, the control unit, in the comparison between the output digital signal and the test digital signal, judges that analog-to-digital conversion functions normally in the device under test when the signals are different only within a predetermined range of numerical values.
In the test system, the control unit, in the comparison between the output digital signal and the test digital signal, judges that analog-to-digital conversion functions normally in the device under test when the signals are different only within a predetermined range of numerical values. Thus, the percentage of devices under test passing a test can be increased by setting the predetermined range appropriately.
A second aspect of the invention is directed to another test system includes a memory tester and pin electronics. The memory tester includes a test pattern generating section for generating a predetermined test pattern to be supplied to a memory cell in each address in a memory device and a control unit for controlling the test pattern generating section. The pin electronics include a first digital-to-analog converter and a first comparator. In the test system, the control unit is supplied with vector data for generating the predetermined test pattern. The test pattern generating section generates the predetermined test pattern on the basis of the vector data. A test digital signal included in the predetermined test pattern is supplied to a device under test having the digital-to-analog converting function. A predetermined digital value designated by the control unit is converted into a first reference analog signal by the first digital-to-analog converter to be input to one input terminal of the first comparator. An output analog signal generated in the device under test by converting the test digital signal is input to the other input terminal of the first comparator. The first comparator compares the output analog signal generated in the device under test with the first reference analog signal, thereby supplying the result of comparison to the control unit as a first result digital signal. And the control unit verifies the digital-to-analog converting function of the device under test on the basis of the first result digital signal.
In the test system, the test digital signal included in the predetermined test pattern is supplied to the device under test having the digital-to-analog converting function. The first comparator compares the output analog signal generated in the device under test with the first reference analog signal, thereby supplying the result of comparison to the control unit as a first result digital signal. The control unit verifies the digital-to-analog converting function of the device under test on the basis of the first result digital signal. This allows the memory tester to perform testing of the digital-to-analog converting function of the device under test.
Preferably, in the test system, the pin electronics further include a second digital-to-analog converter and a second comparator. Another predetermined digital value designated by the control unit is converted into a second reference analog signal by the second digital-to-analog converter to be input to one input terminal of the second comparator. The output analog signal generated in the device under test is input to the other input terminal of the second comparator. The second comparator compares the output analog signal generated in the device under test with the second reference analog signal, thereby supplying the result of comparison to the control unit as a second result digital signal. And the control unit verifies the digital-to-analog converting function of the device under test also on the basis of the second result digital signal.
In the test system, the second comparator compares the output analog signal generated in the device under test with the second reference analog signal, thereby supplying the result of comparison to the control unit as a second result digital signal. The control unit verifies the digital-to-analog converting function of the device under test also on the basis of the second result digital signal. Thus, setting the predetermined digital values different from each other such that the first and second reference analog signals have values different from each other allows the control unit to verify whether the output analog signal generated in the device under test has a value that falls within a range limited by the values of the respective reference analog signals.
A third aspect of the invention is directed to a testing method. The testing method uses a memory tester and a digital-to-analog converter. The memory tester includes a test pattern generating section for generating a predetermined test pattern to be supplied to a memory cell in each address in a memory device and a control unit for controlling the test pattern generating section. The digital-to-analog converter is one of digital-to-analog converters, one built in the memory tester and the other provided outside the memory tester. The testing method includes the steps of: (a) supplying the control unit with vector data; (b) generating the predetermined test pattern; (c) converting a test digital signal included in the predetermined test pattern into a test analog signal by the digital-to-analog converter; and (d) comparing, in the control unit, the test digital signal with an output digital signal generated in the device under test by converting the test analog signal, thereby verifying the analog-to-digital function of the device under test. The vector data is for generating the predetermined test pattern. The predetermined test pattern is generated in the test pattern generating section on the basis of the vector data. The test digital signal is converted to be supplied to a device under test having the analog-to-digital converting function.
With the method, a test digital signal included in the predetermined test pattern is converted into a test analog signal by the digital-to-analog converter to be supplied to the device under test. The control unit compares the test digital signal with the output digital signal generated in the device under test by converting the test analog signal, thereby verifying the analog-to-digital converting function of the device under test. This allows the memory tester to perform testing of the analog-to-digital converting function of the device under test.
Preferably, the testing method further uses a storage device for storing the output digital signal and outputting the signal to the control unit. The testing method further includes the step of (e) storing the output digital signal in the storage device.
With the method, the storage device for storing the output digital signal and outputting the signal to the control unit is further provided. Thus, the control unit does not need to make a real-time comparison between the output digital signal and the test digital signal.
Preferably, in the testing method, the storage device is provided in a fail bit analyzer for analyzing a failure position in the memory device when a failure is found in an output of the memory device.
With the method, the storage device is a memory provided in the FBA. Thus, there is no need to provide an additional storage device for the memory tester, but the memory provided inside the FBA which is generally built in the memory tester can be diverted for the storage device.
Preferably, in the testing method, the control unit, in the comparison between the output digital signal and the test digital signal, judges that analog-to-digital conversion functions normally in the device under test when the signals are different only within a predetermined range of numerical values.
With the method, the control unit, in the comparison between the output digital signal and the test digital signal, judges that analog-to-digital conversion functions normally in the device under test when the signals are different only within a predetermined range of numerical values. Thus, the percentage of devices under test passing a test can be increased by setting the predetermined range appropriately.
A fourth aspect of the invention is directed to another testing method. The testing method uses a memory tester and pin electronics. The memory tester includes a test pattern generating section for generating a predetermined test pattern to be supplied to a memory cell in each address in a memory device and a control unit for controlling the test pattern generating section. The pin electronics include a first digital-to-analog converter and a first comparator. The testing method includes the steps of: (a) supplying the control unit with vector data; (b) generating the predetermined test pattern; and (c) supplying a test digital signal included in the predetermined test pattern to a device under test having the digital-to-analog converting function. The vector data is for generating the predetermined test pattern. The predetermined test pattern is generated in the test pattern generating section on the basis of the vector data. In the testing method, a predetermined digital value designated by the control unit is converted into a first reference analog signal by the first digital-to-analog converter to be input to. one input terminal of the first comparator. An output analog signal generated in the device under test by converting the test digital signal is input to the other input terminal of the first comparator. The first comparator compares the output analog signal generated in the device under test with the first reference analog signal, thereby supplying the result of comparison to the control unit as a first result digital signal. The testing method further includes the step of (d) verifying the digital-to-analog converting function of the device under test in the control unit on the basis of the first result digital signal.
In the method, the test digital signal included in the predetermined test pattern is supplied to the device under test having the digital-to-analog converting function. The first comparator compares the output analog signal generated in the device under test with the first reference analog signal, thereby supplying the result of comparison to the control unit as a first result digital signal. The control unit verifies the digital-to-analog converting function of the device under test on the basis of the first result digital signal. This allows the memory tester to perform testing of the digital-to-analog converting function of the device under test.
Preferably, in the testing method, the pin electronics further include a second digital-to-analog converter and a second comparator. Another predetermined digital value designated by the control unit is converted into a second reference analog signal by the second digital-to-analog converter to be input to one input terminal of the second comparator. The output analog signal of the device under test is input to the other input terminal of the second comparator. The second comparator compares the output analog signal generated in the device under test with the second reference analog signal, thereby supplying the result of comparison to the control unit as a second result digital signal. And the control unit verifies the digital-to-analog converting function of the device under test also on the basis of the second result digital signal, in the step (d).
In the method, the second comparator compares the output analog signal generated in the device under test with the second reference analog signal, thereby supplying the result of comparison to the control unit as a second result digital signal. The control unit verifies the digital-to-analog converting function of the device under test also on the basis of the second result digital signal. Thus, setting the predetermined digital values different from each other such that the first and second reference analog signals have values different from each other allows the control unit to verify whether the output analog signal generated in the device under test has a value that falls within a range limited by the values of the respective reference analog signals.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.